1. Lab 4 Overview
In Lab 3, you placed all the components for your embedded system onto your printed circuit board.
In this lab, you route all of the signals to complete your printed circuit board. In your lab session, you
will perform a design review of your printed circuit board to ensure that you are ready to place an
order to have your PCB manufactured. Routing of the printed circuit board will take a fair amount of
time, so be sure to get started early!
A. Open the Altium Designer Project that you completed in Lab 3 by clicking on the
ECE315.PrjPcb PCB Project File.
B. Printed circuit board manufactures publish a set of manufacturing specifications that you
must follow if you want your printed circuit board to be manufactured at a reasonable cost.
Altium allows you configure a set of design rules to meet these specifications.
The project you have been provided has been configured to meet the manufacturing
requirements for lowest cost PCB manufactures. Watch the video on the course website
related to PCB Design Rules.
C. You are now ready to route the LEDs that were placed for you. DO NOT route the 5.0V and
GND signals connected to the LEDs. You will do that in a later step.
You can watch the PCB Routing Video found on the course website to complete the routing of
You are NOT allowed to use the auto router to complete the routing of the board. Using the
auto router will result in no points being awarded for this lab.
You are NOT allowed to move any of the APA102C LEDs, mounting holes, or capacitors
connected to the APA102C LEDs.
D. You will now define polygons for the signals related to 5.0V and GND. Starting at 11:22 of the
routing video, follow along and create polygons for 5.0V on the top layer and GND on the
Be sure to add vias to connect all of the LEDs’ pad 3 to GND.
3 | UW-Madison ECE Department: Joe Krachey
E. You are now ready to start routing the remaining connections on the PCB (minute 17 of the
video). Here are a few items to consider as you start routing:
Don’t be afraid to rotate/move parts it’s going to make routing the board easier.
Rarely are all parts rotated in the most efficient manner after the first attempt at
Use an orthogonal approach to routing signals. When possible, vertical tracks should
be on the top layer and horizontal tracks should be on the bottom layer. This is going
to help avoid situations where a signal cannot be routed.
If you have an exceptionally long track that create necks in your polygons, you can
add a short length of track on the opposite layer. This is called stitching a signal.
Stitching ensures that your polygons have good electrical connectivity and provide an
adequate current return path.
F. Watch Adding Additional Text and Images video on the course website to see how to add your
contact info to the PCB. I would suggest that the font size of your name is at least 120 mils.
The rest of your contact information should be at least 100 mils.
G. Add ON/OFF text to the bottom silk screen of the board to indicate when power is being
supplied by the battery.
H. Run a Design Rule check to verify that you have routed all of your nets and to find other
issues that many lead to a non-functional PCB. You can run the design rule check from the
PCB editor from ToolsDesign Rule Check. You will want a report that lists 0 errors and 0
4 | UW-Madison ECE Department: Joe Krachey
3. Pre Lab: What to Turn in
File Name Description
LastName_FirstName_Lab4_Altium.zip Altium Project ZIP file. All schematic pages
should be completed, all parts are placed,
routing is completed, contact information has
been added, and the Design Rule Check results
in 0 errors.
LastName_FirstName_Lab4_Sch.pdf Color PDF containing all the sheets in your
Use FileSmart PDF to generate the
schematics. You can use the default settings,
but only include the .SchDocs on the 3rd page
of the dialog
LastName_FirstName_Lab4_Layers.pdf Use Snipping Tool to capture the top and
bottom layers of the board when you are in
Single Layer mode (shift s).
Use Snipping Tool to capture the top and
bottom layers of the board when you are in 3D
Use WORD to generate a single PDF with each
layer on a separate page.
5 | UW-Madison ECE Department: Joe Krachey
4. Lab Work
A. Your TA will assign groups of three people to perform a design review of your final .PcbDoc.
The purpose of the design review is to help ensure that your design is ready to be fabricated.
During the design review process, each of the designs will be examined using the check list
found at the end of this document.
B. Once you have fixed any issues found in the design review, use Generating BOM and Build
Files video to generate gerber files, NC Drill files, final schematics, and a BOM for your board.
C. If you do not have an account with Digikey, you will need to register an account with Digikey
and order all the parts in your BOM. See the video related to this on the class website.
I would highly suggest ordering some extra parts. It is easy to lose the capacitors and
resistors that you are placing, so order 10 extra capacitors.
If you are ordering as a group of 3+ students, I would also suggest that the group orders at
least 1 extra of all your parts. If your board does not function correctly, you can use the extra
parts to build a functional board using a known good PCB provided to you.
D. Order 10 copies of your PCB from PCBWay. The Ordering Parts and PCB video will
demonstrate how to order the parts and printed circuit board.
NOTE: You can save on shipping if you order in groups. One student will need to have the ZIP
files with the gerbers and NC drill files for each student sharing the shipping cost. That
student will upload and quote each card separately, but when you pay for the boards, you can
choose to ship them together.
6 | UW-Madison ECE Department: Joe Krachey
5. Post Lab: What to Turn in
File Name Description
LastName_FirstName_Lab4_Altium.zip Altium Project ZIP file. All
schematic pages should be
completed, all parts are placed,
routing is completed, contact
information has been added, and
the Design Rule Check results in 0
LastName_FirstName_Lab4_Sch.pdf Color PDF containing all the sheets
in your design.
Use FileSmart PDF to generate
the schematics. You can use the
default settings, but only include
the .SchDocs on the 3rd page of
LastName_FirstName_Lab4_Layers.pdf Use Snipping Tool to capture the
top and bottom layers of the board
when you are in Single Layer mode
Use Snipping Tool to capture the
top and bottom layers of the board
when you are in 3D mode (3).
Use WORD to generate a single PDF
with each layer on a separate page.
7 | UW-Madison ECE Department: Joe Krachey
LastName_FirstName_Lab4_BOM.xlsx The BOM generated by Altium.
Each part should contain the
quantity and manufacturer part
LastName_FirstName_Lab4_Orders.pdf Use WORD to generate a single PDF
with the following items:
Use Snipping Tool to capture a
picture of your Digikey Invoice after
you have purchased your parts.
Use Snipping Tool to capture the
production status from PCB Way
after you have paid for your printed
A PDF (or .jpg/png) of the
completed design review. The
image must have signatures
Use Snipping Tool to capture an
image of the resign rule check
showing no errors or warnings.
8 | UW-Madison ECE Department: Joe Krachey
6. Design Review Check List
Schematic Requirements Completed
1 All Nets have net names
2 All parts have a unique reference designators
3 All parts have supplier links that include the manufacturer and part num.
4 Reference Designators are clearly visible and do not overlap.
5 All integrated circuits have a 1uF bypass capacitor on EACH supply pin.
6 Programming header has the correct nets on each pin
7 MCU has the programming interface connected correctly.
8 MCU has power and ground applied to the correct pins.
9 MCU has the SPI interface correctly connected to the APA102C LEDs
10 MCU has the UART interface correctly connected to the MPC2221A
11 The piezo buzzer is connected to a GPIO pin on the MCU
12 All unused pins should be marked with No ERC Connectors
PCB Requirements Completed
1 Bypass Capacitors within 200 mils to the pin they service.
2 Power signals like 3v3 should be carried by very thick traces (25-
200mils) or preferably by dedicated polygon pours/planes.
3 No conductive material within 50 mils of the board edge.
4 There should be a 10 mil trace on mechanical layer 2 that defines the
5 Minimum hole size set to 15 mils
6 Minimum annular ring of 6 mils on all vias and through hole parts.
7 All nets are routed
8 Polygon pours used to route 5.0V and GND.
9 Contact information has been placed on the PCB
10 Reference designators for each part clearly indicate which part they are
11 All test points have a text string in a silk screen layer indicating what net
they are connected to.
12 Design passes Design Rule Check with 0 errors and 0 warnings
Originating Engineer Signature : __________________________________________________
Reviewer #1 Signature :___________________________________________________
Reviewer #2 Signature :___________________________________________________