Description
Assume that only the NOT gate, and the 2-input AND, OR and NAND gates are
available.
1. Consider the following Boolean function:
𝐹(𝑊, 𝑋, 𝑌, 𝑍) = ∑ 𝑚(1, 3,4,7,8,10,11) + ∑ 𝑑(6,12,13,14,15)
Derive the minimal sum-of-products (MSOP) expression for F, and design
the logic gate circuit for F using (a) AND, OR and NOT gates, and (b) NAND
gates only. Test the circuit for all combinations of input variables.
2. 4-to-2 bit encoder: Inputs (1000, 0100, 0010, 0001) with expected outputs
as (00, 01, 10, 11) respectively
3. 4-to-2 bit priority encoder: Inputs (1xxx, 01xx, 001x, 0001) with expected
outputs as (00, 01, 10, 11) respectively. x can be 0 or 1.
4. 2-to-4 bit decoder: Inputs (00, 01, 10, 11) with expected outputs as (1000,
0100, 0010, 0001) respectively
5. 3-to-8 bit decoder: Inputs (000, 001, 010, 011, 100, 101, 110, 111) with
expected outputs as (10000000, 01000000, 00100000, 00010000,
00001000, 00000100, 00000010, 00000001) respectively.