Description
2 Overview
In this timed lab, you will be creating an ALU with four operations. This ALU will take in two 8-bit
inputs and one 2-bit op code. It will output one 8-bit output.
2.1 Tasks and Strategy
• Set up your MUX for the ALU output.
• Build your first operation circuit, and connect it to the MUX. Then submit it to Gradescope.
• Build your second operation circuit and connect it to the MUX. Submit it to Gradescope.
• Rinse and repeat (do operations 3 and 4).
• Hint: After you complete each operation, you may want to save a local copy of your file as a backup.
That way, if you have a problem later on, you can revert to the prior working version quickly.
2.2 Allowed Components
When building this ALU, you may only use:
1. basic logic gates (AND, OR, NOT),
2. decoders,
3. multiplexers,
4. the built-in Circuitsim adders (NOT the built-in subtractors),
5. splitters,
6. wires,
7. tunnels,
8. constants,
9. input pins,
10. output pins
IMPORTANT NOTE 1: YOU DO NOT NEED TO BUILD THE GATES OUT OF TRANSISTORS.
PLEASE, FOR YOUR OWN SAKE, DON’T DO IT. USE THE BUILT IN GATES.
IMPORTANT NOTE 2: You’re allowed to use CircuitSim’s default, built-in adders (in the Arithmetic
tab). So please don’t try to make your own adders, just use that one. You’re not allowed to use anything
else from the Arithmetic tab (don’t try to use a subtractor; if you need a subtractor, you will need to create
your own using the above-mentioned components).
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3 Instructions
3.1 CircuitSim Information
For this assignment, you will be using CircuitSim. The version is the exact same as the one used in Homework
2 and 3, and can be found on the Docker image provided for this class. To ensure you are on the correct
version, check to see if the title bar says ”CircuitSim v1.8.2 2110 edition”. If your file does not open in
this version of CircuitSim you will receive a 0. All changes should be made in the tl1.sim file. Do
not move or rename any or the input or output pins.
3.2 ALU Components
You will create an 8-bit ALU with the following operations, using any of the gates listed above. All numbers
should be interpreted as 2’s complement.
00. A / 4 [A / 4]
01. absOf(A + B) [(A + B) < 0, return -(A + B), (A + B) >= 0, return (A + B)]
10. XNOR [A XNOR B]
11. oddAndEven [Ex. A = 10111011, B = 01011010, output = 10111010]
see below for details
Below are descriptions to elaborate more on the problems above. If you’re still having trouble comprehending
exactly what the question is asking after reading below, please ask one of your TAs for clarification.
• In the A / 4 operation, note that for A, our test cases will ALWAYS have a number divisible by 4.
• Notice that A / 4 depends solely on the A input. It should NOT rely on B being a particular
value.
• For the absOf(A + B) operation, you need to return the absolute value of A + B. That is, if A + B
< 0, as in A + B is negative, return -(A + B). If A + B >= 0, as in A + B is positive or zero, simply
return A + B.
• HINT: The truth table for the XNOR operation is as follows:
• oddAndEven should return an output where the even bits of the output correspond to the AND of
the even bits of A and B. The odd bits correspond to the OR of the odd bits of A and B. For example,
if A = 10111011 and B = 01011010, the output should be 10111010. In the output, the bits at the
even positions (at positions 6(0), 4(1), 2(0) and 0(0) respectively) are from 0101 & 1100, and the bits
at the odd positions (at positions 7(1), 5(1), 3(1) and 1(1) respectively) are from 1111 + 0011.
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• This ALU has two 8-bit inputs for A and B and one 2-bit input for OP, the op-code for the operation
in the list above. It has one 8-bit output named out.
• The provided autograder will check the op-codes according to the order listed above A / 4 (00), absOf(A
+ B) (01), etc. and thus it is important that the operations are in this exact order.
4 Checking your work
You can locally check your grade by navigating to the directory containing tl1.sim and running
java -jar tl1-tester.jar
5 Deliverables
Please upload the following files onto the assignment on Gradescope:
1. tl1.sim
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