Description
• Read and follow the Icarus Verilog Getting Started Guide at http://iverilog.wikia.com/wiki/Getting Started
• Read and follow the GTKWave introduction at http://iverilog.wikia.com/wiki/GTKWAVE
• After you have an understanding of the Verilog HDL and the Icarus Verilog and GTKWave tools,
implement a two-bit adder in Verilog
– Use dataflow modeling for your implementation (primitives and operators only)
– A two-bit adder takes in two two-bit values and produces a three-bit result, as follows:
A1 A0 B1 B0 C S1 S0
0 0 0 0 0 0 0
0 0 0 1 0 0 1
0 0 1 0 0 1 0
0 0 1 1 0 1 1
0 1 0 0 0 0 1
0 1 0 1 0 1 0
0 1 1 0 0 1 1
0 1 1 1 1 0 0
1 0 0 0 0 1 0
1 0 0 1 0 1 1
1 0 1 0 1 0 0
1 0 1 1 1 0 1
1 1 0 0 0 1 1
1 1 0 1 1 0 0
1 1 1 0 1 0 1
1 1 1 1 1 1 0
• Test your adder using Icarus Verilog and GTKWave, which should involve creating a testbench for
your adder
The report for this lab should include the following sections:
1. Description/Objectives
2. Procedure, which must include
(a) A screenshot from GTKWave showing correct operation of your adder
3. Observations
4. Conclusions
5. Appendix
(a) The Verilog code for your adder (not your testbench)
