Description
1. Use VHDL to build a positive-edge-triggered D flip-flop with switch sw0 as input D, button btnC as CLK input, LED led0 as
output Q, and LED led1 as output Q’. [30 marks]
2. To build the divide-by-2 counter as shown below, reuse the D flip-flop module in question 1 by using the hierarchical design
method. In this part, hardware implementation and demo video are NOT required, build a testbench to observe the waveforms
of the input and output, and capture the entire screen of Vivado with the simulation waveforms for submission.
[30 marks]
Hints
a. Some antivirus software may stop the simulation process of Vivado, so disabling the antivirus software is preferable.
b. Since the Q’ feed back to the input D, it cannot be initialized in the testbench. It should be initialized in the VHDL of the
divide-by-2 counter.
c. For setting up the testbench, please refer to the example in Lec00b VHDL First Example Using Vivado and Basys3. The
output will be something like shown below:
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