Description
Problem Statement: DRAM Request Manager for Multicore Processors
In this assignment you will extend your earlier DRAM request manager to the multicore CPU
case. Our architecture now consists of N CPU cores, each running a different MIPS program,
and sending DRAM requests to a Memory Request Manager which interfaces with the DRAM
(see figure). The DRAM has the same properties that you have already implemented in earlier
assignments. See example below.
1. Extend your earlier MIPS simulator (with DRAM timings) to the multicore scenario.
Your objective is to implement the Memory Request Manager in such a way that the
instruction throughput (total number of instructions completed by the whole
system in a given period, say from Cycle 0 to Cycle M) is maximised.
2. Estimate the delay (in clock cycles) of your own Memory Request Manager
algorithm and incorporate it into your timing model. Justify the estimation.
Remember this is an estimate. You don’t have to design the entire manager
hardware.
Input:
1. Parameter N (number of CPU cores).
2. Parameter M (simulation time: number of cycles). Execution stops after the
simulation time, even though all the instructions may not have completed.
3. MIPS assembly language files t1.txt, t2.txt,…,tN.txt
4. DRAM timing values, as in earlier assignments.
Output:
1. Include an option to print out the activity in the system at every clock cycle.
2. After execution completes, print the relevant statistics individually for each CPU.
Example:
Assume the following:
1. Programs running in the different CPU cores are independent of each other.
2. Instructions themselves are not accessed from the DRAM. Only lw/sw instructions result
in DRAM accesses.
3. Use the same architectural and ISA assumptions as in Assignment 3.
Test cases [IMPORTANT]: Carefully design and document the scenarios you will use to
evaluate your implementation. This will be evaluated.
Marks Distribution:
1. Multicore functionality [7 Marks]
2. Throughput efficiency [5 Marks]
3. Delay estimation and its incorporation [5 Marks]
4. Comprehensiveness of testing [5 Marks]
5. Documentation [3 Marks]
